The present invention relates to a semiconductor device which is advantageous to a fine formation, and specifically to an improvement of a contact technique and an interconnecting technique for a non-volatile semiconductor storage.
The fine formation of a semiconductor element is important to accomplish a large capacity and a high speed of the semiconductor device, specifically a semiconductor memory. This demand is significant for the large-capacity semiconductor memory such as a DRAM and an EEPROM.
The EEPROM is a non-volatile semiconductor memory in which data can be electrically rewritten. Known is the EEPROM using a memory cell of a MOS transistor structure having a stacked layer structure having a charge storage layer and a control gate.
FIGS. 1 and 2 show the structure of the memory cell of the EEPROM having a general MOS type FET arrangement. FIG. 1 is a plan view. FIG. 2 is a cross sectional view taken on line F2--F2 of FIG. 1.
An element separating/insulating film 17 is formed on a P-type silicon substrate or P-well 16. Under the film 17, a P.sup.+ -type layer 15 is formed as a channel stopper in the P-well 16. In such a manner, a thin first gate insulating film 18, which a tunnel current can flow through, is formed over a channel region surface on the P-type silicon substrate or P-well 16 in which the element is separated by a selective oxidation (LOCOS element separation).
A charge storage layer 19 is formed on this insulating film 18. A control gate 21 is also formed on this layer 19 through a second gate insulating film 20. The charge storage layer 19 and the control gate 21 are sequentially etched by the use of the same mask in a channel longitudinal direction, whereby their edges are arranged. These stacked gates 19 and 21 are then used as the mask so that an impurity is ion-implanted. An N.sup.+ -type layer 22 to be a source and a drain is thus formed.
FIG. 3 is a cross sectional view when a trench element separation is used. This cross section corresponds to a portion to be compared to a sectional portion of the cross sectional view shown in FIG. 2. A trench groove 17 for separating the element is formed on the P-type silicon substrate or P-well 16. An insulating material for use in the element separation, for example, an SiO.sub.2 member 14 is buried in the trench groove 17.
A P.sup.+ -type layer 13 is formed as the channel stopper in a lower portion of the trench groove 17. In such a manner, the thin first gate insulating film 18, which the tunnel current can flow through, is formed over the channel region surface on the P-type silicon substrate or P-well 16 in which the element is separated by the trench groove 17. The charge storage layer 19 is formed on this insulating film 18. The control gate 21 is also formed on this layer 19 through the second gate insulating film 20.
The trench element separation is used, whereby the fine formation can be expected in a direction parallel to the control gate.
In a non-volatile semiconductor memory device using the memory cell as described above, the memory cells are arranged in series or in parallel, whereby some memory cell array arrangements are proposed and well known.
FIG. 4 is a plan view showing a conventional NOR type cell arrangement as an example of the memory cell array arrangements. The NOR type cell is arranged in the following manner. That is, the cells are connected in parallel to each other so that the drains of two memory cells 41a, 41b may be used in common, and the cells are arranged so that a bit line contact 42 may exist on a parallel connecting point.
In the above-described NOR type cell arrangement, a bit line contact portion is disposed on the semiconductor substrate in which the element is separated. The bit line contact portion is shared with two cell transistors. The element is not separated on a source side of the one cell transistor so that it is defined as a common interconnection (diffusion source region) 46.
This diffusion source region 46 is connected to a source line 48 through a source line contact 47.
The region of the bit line contact (drain contact) 42 and the diffusion source region 46 are N-type which is a polarity opposite to the above-mentioned semiconductor substrate or P-type well in which the cell transistor is disposed. The regions are doped with the impurity so that the impurity concentration thereof may reach a desired value as required.
In the NOR type cell, a write into the charge storage layer 19 by an electronic implantation is accomplished by the following procedure. For example, potentials of 10V and 5V are applied to a control gate (word line) 44 and a drain (bit line) 45, respectively. A channel hot electron is then generated by a transverse high electric field near the drain. This hot electron is implanted.
On the other hand, an erase operation by removal of the electron from the charge storage layer 19 is accomplished by the following procedure. For example, the potentials of 0V and 12V are applied to the control gate (word line) 44 and the source region (from the source line to the source diffusion region) 46, respectively. An F-N (Fowler-Nordheim) tunneling is then performed between the charge storage layer 19 overlapping with the source region and the source region 46.
In the memory cell array of such a NOR type cell arrangement, in order to accomplish the high speed and the large capacity, the fine formation by a reduction of dimension is strongly desired. The above-described trench element separation is effective for the fine formation in the longitudinal direction in which the control gate is arranged.
On the other hand, the reduction of a control gate length and a space between the control gates is very important for the fine formation in a direction perpendicular to the longitudinal direction in which the control gate 44 is arranged, that is, in the longitudinal direction in which the bit line 45 is arranged.
In the diffusion source region 46, the formation of a common source line in parallel to the control gate 44 and between the control gates 44 causes a significant problem for the fine formation of the memory cell. For example, assuming that a minimum dimension is 0.25 .mu.m, the element separating region 43 has a longitudinal width of an addition of the word line (control gate) length of the two memory cells 41a, 41b, the width of the bit line contact 42 and an allowance between the control gate 44 and the bit line contact 42. For example, assuming that the control gate length is 0.25 .mu.m, the bit line contact is 0.3 .mu.m in size and the allowance between the bit line contact 42 and the control gate 44 is 0.15 .mu.m, the longitudinal width of the element separating region 46 is 1.1 .mu.m.
On the other hand, the width of an element separating region 43 in a short direction is equal to the width of the element separating region, for example, 0.25 .mu.m. It is very difficult to transfer such a fine pattern by the use of a lithography technique and to form a thick field insulating film or the trench groove. An influence such as a proximity effect and a resist stretch causes a pattern distortion.
More specifically, the distortion of the longitudinal dimension of the gate causes a difference in dimension between the diffusion source region 46 and the control gate 44. This may thus cause a variation in a threshold voltage contributing to the variation in the erase operation or the like. This is a serious problem.
In order to solve such a problem, a Self-Aligned-Source (SAS) method has been heretofore used. FIGS. 5 and 6 are cross sectional views taken on line F5/6--F5/6 of FIG. 4. FIGS. 5 and 6 show an example of the memory cell array in case of using the SAS method.
An element separating film 50 (SiO.sub.2) to be the element separating region is disposed parallel to a direction of the bit line. A charge storage layer 51 (F. G.: a floating gate), a gate insulating film 52 (ONO: a three-layer structure constituted by oxide film/nitride film/oxide film) and a control gate (word line) 53 (a stacked layer structure constituted by polysilicon (POLY) and WSi) are then formed.
At this time, a mask material 54 other than SiO.sub.2, for example, SiN is disposed on the control gate 53. After the control gate 53 is formed, the whole surface is coated with a resist 55. The region for forming the common source line is opened by the lithography and thus an opening 56 is formed.
As shown in FIG. 6, a dry etching is performed by the use of a RIE condition of SiO.sub.2 having a higher selectivity ratio with respect to the mask 54 (SiN and Si), whereby the element separating film 50 in the opening is removed. The condition of higher selectivity ratio allows the element separating film 50 to be removed without grinding the control gate 53 and the semiconductor substrate. The diffusion source region 56 can be thus formed in such a manner that the region 56 and the control gate 53 are not misaligned.
After the etching, a resist pattern is formed so that the diffusion source region 56 may be opened again by the lithography technique. An N-type impurity such as phosphorous and arsenic is ion-implanted, whereby the common diffusion source region 56 is formed.
The use of the SAS method permits the fine formation in the direction of the bit line.
However, in the SAS method, once the element is separated, the element separating film 50 is partially removed. The ion implantation of the impurity is then performed, whereby the diffusion source region 56 is formed. Thus, when a trench element separating method is used, it is difficult to form the source line. In the aforementioned NOR type cell, a writing method employing a channel hot electron implantation is generally used. A punch-through pressure resistance between the trench-element-separated bit line contacts is therefore required to be higher than the voltage (about 6V) applied to a drain portion of the memory cell during the write operation. Thus, the trench groove must have a depth (300-400 nm) similar to a thickness of a field oxide film formed by the conventional selective oxidation, the so-called LOCOS element separation. After the removal of SiO.sub.2 in the trench groove, the trench groove has a difference in level of one depth of the trench groove. Thus, even if the ion implantation is performed, a problem occurs in which the source line is not formed.
Furthermore, when a 0.25 .mu.m rule is used, the control gate length is about 0.25 .mu.m. Thus, when the high-concentration impurity of 1.times.10.sup.15 cm.sup.-2 or more is ion-implanted into the source region so as to self-match with the control gate, the impurity is diffused under the control gate due to a heat treatment after the implantation. As a result, an effective channel length becomes shorter. Thus, another problem occurs in which punch through is caused. The ion-implantation of the high-concentration impurity into the source line is therefore expected to be very difficult. This causes a difficulty in forming the source line and an increase of a source line resistance. A further problem such as the reduction of a cell current and the variation in the threshold voltage occurs.
FIG. 7 is a plan view showing the arrangement of a NAND type cell in which a plurality of memory cells are connected in series so that they may share the source and drain diffusion layers thereof.
The NAND type cell arrangement can reduce an area occupied by the cell so that the area may be smaller than the area of the above-described NOR type cell arrangement (for example, Jpn. Pat. Appln. KOKAI Publication No. 63-268193).
In a single NAND cell group in which memory cell transistors MC1 to MC8 are connected in series, the element is linearly separated along the direction of the bit line. A hatched portion shows the charge storage layer (floating gate FG) 19 under the control gate (word line) 21. A drain D on one end of the single NAND cell group is connected to the bit line (not shown) through a select gate transistor SG1 (a bit line contact BC). The source on the other side thereof is connected to a diffusion source line S through another select gate transistor SG2.
One bit line contact BC is disposed in each NAND cell group. In the diffusion source line, the element is not separated, and all the NAND cell groups are connected to each other by the common source line.
In the memory cell of the NAND type cell arrangement, both of the erase and the write operations use an exchange of charge between the charge storage layer and the substrate.
FIG. 8 shows a non-selected bit line Vm8 applying type program. FIG. 9 shows an operating potential relationship of the memory cell array of the NAND cell arrangement and shows a non-selected bit line floating type program.
An erasing operation is performed in the following manner. That is, in FIGS. 8 and 9, a low potential (for example, 0V) is applied to the control gate in the same and common manner. A high potential (for example, 20V) is applied to the source, the drain and the substrate. By the use of a tunnel phenomenon, the electron is discharged from the charge storage layer 19. The threshold voltage reaches a negative value, whereby the cell is changed into, for example, a "0" state.
On the other hand, at the time of the write into the gate, the high potential (for example, 20V) is applied to the control gate. The low potential (for example, 0V) is applied to the source, the drain and the substrate. The electron is implanted into the charge storage layer. The threshold voltage reaches a positive value, whereby the cell is changed into, for example, a "1" state.
In the NAND type cell arrangement, the write is simultaneously performed in all the transistors linked to the selected control gate. Accordingly, a "1" write cell for making the threshold voltage positive and a "0" write cell for leaving the threshold voltage negative are linked to the same control gate. In order to allow such a write to have selectivity, a writing method as described below is used.
In FIG. 8, the potential of 0V is applied to a bit line BL1 of the selected cell for the "1" write. An intermediate potential (for example, 8V) is applied to the bit line of the selected cell for the "0" write.
In order to transfer the intermediate potential to the selected cell, the voltage (for example, 10V) higher than an intermediate voltage is applied to the non-selected control gate. The voltage of 0V is applied to the gate of the select transistor on the source line side. At the time of the write, a through current passing between the bit line and the source line is caused to be absent so as to thereby improve a pressurizing ability of a peripheral pressurizing circuit for generating the intermediate voltage.
On the other hand, the voltage of 10V is applied to the gate of the select transistor on the bit line side in the same manner as the non-selected control gate, whereby the intermediate potential is transferred.
In FIG. 9, the low voltage (for example, 3V) is applied to the gate of the select transistor on the bit line side of the bit line for the "0" write. The low voltage (for example, 3V) is also applied to the bit line. In such a manner, a method of cutting off the select transistor is adopted.
The select transistor on the source side is cut off in the same manner in FIG. 8, whereby the whole bit line is changed into a floating state. In this state, when the high voltage (for example, 20V) is applied to the selected control gate, the potential of the control gate allows a channel potential of the non-selected cell for the "0" write to be also increased by a capacity coupling. The electric field applied to the non-selected cell for the "0" write is reduced, whereby the "1" write is suppressed. In order to effectively increase the channel potential of the non-selected cell for the "0" write, the intermediate potential (for example, 8V) is also applied to the non-selected control gate.
A read of data is accomplished by the use of the positive and negative values of the threshold voltage in the "1" and "0" states.
That is, the low potential (for example, 0V) is applied to the source and the selected control gate. The potential for the read (for example, 1V) is applied to the selected bit line BL1. Whether the state is "0" or "1" is determined in accordance with the presence of absence of the current passing through the cell transistor.
At this time, the voltage (for example, 5V) higher than the threshold voltage of the "1"-state cell transistor is applied to all the non-selected control gates so that all the non-selected cells linked to the selected bit line may be in an ON state.
As described above, in the EEPROM, the data erase and write is accomplished by the use of the tunnel current in the oxide film between the charge storage layer and the substrate. The channel is formed on an interface between the oxide film and the substrate just below the charge storage layer in the same manner, whereby the data is written.
In such a NAND type cell array arrangement, compared to the NOR type cell array arrangement, a single bit line contact may be disposed for some memory cells (for example, 16 memory cells). The area of a contact region is therefore reduced. Thus, a cell area can be significantly reduced. In other words, the NAND type cell array arrangement is intrinsically superior in the fine formation in the direction of the bit line.
Furthermore, if the trench element separation is used, it is possible to form the memory cell having the very small cell area. As described in "S. Aritome et al.: IEEE Tech. Dig. of IEDM, p. 61, 1994", in the trench-element-separated NAND cell, assuming that the rule is defined so that the minimum dimension may be 0.25 .mu.m, the cell area can be reduced to 0.31 .mu.m.sup.2.
However, in the NAND type cell array arrangement, for example, the 0.25 .mu.m rule is used. In this case, when the diffusion source line is doped with high-concentration impurity, the punch-through pressure resistance of the select transistor adjacent to the diffusion source line is considerably reduced. This causes the problem in which the transistor cannot be cut off during the write. Thus, it is necessary to limit a doping of the high-concentration impurity. The increase of the source line resistance cannot be avoided as is the case with the NOR type cell.
In the NAND type cell array, when the resistance of the diffusion source line becomes higher, a drop of the potential cannot be ignored on the diffusion source line. This causes a spread of threshold voltage distribution during the read. The diffusion source line is replaced by a metal bypass for some NAND arrays each, whereby it is wired. The interconnecting is carried out in order to reduce the resistance of the diffusion source line. However, since the metallic bit line exists on each NAND array, the contact cannot be disposed in each NAND array so as to shunt from the diffusion source line. Thus, the NAND array farthest from a shunt region is most significantly influenced by the resistance of the source line.
That is, during the write, if the selected memory cell in the above-mentioned NAND array is the earliest cell in the memory cells to be written, when the data is written in the earliest cell so as to thereby be in the "1" state, other cells remain "0" state. At this time, due to a verify read, the cell current of the NAND arrays other than the above-described NAND array is much greater than the cell current of the above-described NAND array. Therefore, a source potential of the above-described NAND array is reduced due to the source resistance and the cell current.
Thus, the threshold voltage of the selected cell in the above-described NAND array is apparently higher. Consequently, the write is completed at the voltage lower than the threshold voltage at which the write should be completed. This causes the spread of the threshold voltage distribution after the write.
Such a problem causes another problem described below. That is, when the two or more threshold voltages are set after the write into one memory cell whereby a multi-valued system is used so that one memory cell may have binary or more information, if the spread of the one threshold voltage distribution is larger, a writing voltage and a reading voltage become very high. This causes problems such as the considerable reduction of writing velocity and a disturbance of the cell.
It should be noted that the above-described diffusion source line may be generally referred to as a common signal line of the cell array. Therefore, the above problem is not limited to the non-volatile semiconductor memory device but relates to the semiconductor memory device or the general semiconductor device including the common signal line of the cell array. The array arrangement is not limited to the NOR type cell arrangement and the NAND type cell arrangement. Although the 0.25 .mu.m rule is herein described, the present invention is not limited to this rule.